1. Field of the Invention
The invention relates to memory integrated circuits. It can be applied notably to electrically programmable read-only memories.
The memories are formed by networks of memory cells arranged in lines and columns. The addressing is done, for example, linewise and the reading is done columnwise. A word line is used to address a set of cells located on one and the same line and connected to this word line. The state of the cell is read on a conductor called a "bit line". This conductor is connected to a set of cells positioned along the same column of the network.
The state of a cell is read as follows: a decoder is used to select the line in which the cell is located, and the bit line corresponding to this cell is connected to a read amplifier. The reading is most usually done in two stages:
firstly, the bit line is pre-charged at a determined potential, for example about one volt; PA1 secondly, the cell receives the appropriate voltages and consumes or does not consume current depending on its state (blank or programmed), the consequence of which is that it causes the variation of a potential AD at the output of a current/voltage converter.
The reading is done by comparison of the value AD and of the corresponding value given by a reference circuit connected to a blank cell.
The memory integrated circuits of this type therefore comprise a pre-charging circuit associated with the bit lines.
2. Description of the Prior Art
In the simplest prior art embodiments, the pre-charging circuit is constituted as in FIG. 1. It is connected between the bit line BL and a differential reading amplifier. It is used both to establish a pre-charging potential on the bit line and to send a signal to the reading amplifier. It can therefore be called a pre-charging and reading circuit.
This circuit is a so-called "i/v circuit". It is a current-voltage converter that gives a voltage which varies greatly with the input current. It detects the current absorbed by the cell at the instant of reading (the current depending on the memorization state of the cell). The output voltage of the circuit, highly dependent on the input current, is applied to the differential reading amplifier which flips in a certain direction depending on the state of the cell. During the pre-charging, before the reading, it is the same circuit that imposes a fixed pre-charging voltage on the bit line.
The circuit of FIG. 1 comprises a pre-charging transistor Tp having its drain connected to the supply voltage Vcc of the circuit and its source looped to its gate through an inverter I1 to set up a servo-control system imposing a fixed voltage on the source of the transistor Tp. The inverter I1 is herein constituted by two complementary MOS transistors having their gates joined together to constitute the input of the inverter, said input being connected to the source of Tp, and having their drains connected together to constitute the output of the inverter, said output being connected to the gate of Tp. The characteristics (threshold voltage and dimensions) of the pre-charging transistor Tp and those of the transistors of the inverter fix the value of the pre-charging voltage that the i/v circuit tends to impose on the bit line during the pre-charging operation.
The source of the transistor Tp constitutes the input of the i/v converter and it is connected to the bit line BL by means of transistors which are furthermore needed for the working of the memory: these are notably a read control transistor Tc and a transistor Td for the decoding of the bit line. A transistor Ts, having its source and its gate connected to the source and to the gate of the transistor Tp and being of the same type (N channel in this case) as Tp copies the current in the transistor Tp. The transistor Ts is in series with a transistor Tr mounted as a resistor and connected to the supply voltage Vcc. Tr is preferably a P channel transistor having its gate connected to its drain. The output of the converter is the junction point of the drains of the transistors Tr and Ts and gives a potential AD representing the current consumed by the transistor Tp, namely the current consumed on the bit line BL.
During the pre-charging stage, the transistors Tc and Td are conductive and behave like resistors. The bit line BL behaves like a capacitance with a relatively high value because all of the memory cells of an entire column are connected in parallel to this bit line. The result thereof is that the bit line gets precharged relatively slowly, tending exponentially towards the set value dictated by the transistor Tp and its looping inverter.
The slowness of the pre-charging operation is a drawback since it diminishes the overall access time for the reading of a memory cell. For a memory with an access time of 80 nanoseconds, the pre-charging time may last 25 nanoseconds, for example. It would be desirable to reduce this pre-charging time, either to have more time available for the reading proper or to reduce the total access time.